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Predication (computer architecture)

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</style><div role="note" class="hatnote navigation-not-searchable">Not to be confused with <a href="Branch_prediction" class="mw-redirect" title="Branch prediction">branch prediction</a>.</div>

In <a href="Computer_architecture" title="Computer architecture">computer architecture</a>, predication is a feature that provides an alternative to <a href="Conditional_(computer_programming)" title="Conditional (computer programming)">conditional</a> transfer of <a href="Control_flow" title="Control flow">control</a>, as implemented by conditional <a href="Branch_(computer_science)" title="Branch (computer science)">branch</a> machine <a href="Instruction_(computer_science)" class="mw-redirect" title="Instruction (computer science)">instructions</a>. Predication works by having conditional (predicated) non-branch instructions associated with a predicate, a <a href="Boolean_data_type" title="Boolean data type">Boolean value</a> used by the instruction to control whether the instruction is allowed to modify the architectural state or not. If the predicate specified in the instruction is true, the instruction modifies the architectural state; otherwise, the architectural state is unchanged. For example, a predicated move instruction (a conditional move) will only modify the destination if the predicate is true. Thus, instead of using a conditional branch to select an instruction or a sequence of instructions to <a href="Execution_(computing)" title="Execution (computing)">execute</a> based on the predicate that controls whether the branch occurs, the instructions to be executed are associated with that predicate, so that they will be executed, or not executed, based on whether that predicate is true or false.<a href="#cite_note-rvinyard-1">[1]</a>

<a href="Vector_processors" class="mw-redirect" title="Vector processors">Vector processors</a>, some <a href="SIMD" class="mw-redirect" title="SIMD">SIMD</a> ISAs (such as <a href="AVX2" class="mw-redirect" title="AVX2">AVX2</a> and <a href="AVX-512" title="AVX-512">AVX-512</a>) and <a href="GPU" class="mw-redirect" title="GPU">GPUs</a> in general make heavy use of predication, applying one bit of a conditional mask vector to the corresponding elements in the vector registers being processed, whereas scalar predication in scalar instruction sets only need the one predicate bit. Where predicate masks become particularly powerful in <a href="Vector_processing" class="mw-redirect" title="Vector processing">vector processing</a> is if an array of <a href="Condition_code_register" class="mw-redirect" title="Condition code register">condition codes</a>, one per vector element, may feed back into predicate masks that are then applied to subsequent vector instructions.

<div class="mw-heading mw-heading2"><h2 id="Overview">Overview</h2></div>

Most <a href="Computer_program" title="Computer program">computer programs</a> contain <a href="Conditional_(computer_programming)" title="Conditional (computer programming)">conditional</a> code, which will be executed only under specific conditions depending on factors that cannot be determined beforehand, for example depending on user input. As the majority of <a href="Central_processing_unit" title="Central processing unit">processors</a> simply execute the next <a href="Instruction_(computer_science)" class="mw-redirect" title="Instruction (computer science)">instruction</a> in a sequence, the traditional solution is to insert branch instructions that allow a program to conditionally branch to a different section of code, thus changing the next step in the sequence. This was sufficient until designers began improving performance by implementing <a href="Instruction_pipelining" title="Instruction pipelining">instruction pipelining</a>, a method which is slowed down by branches. For a more thorough description of the problems which arose, and a popular solution, see <a href="Branch_predictor" title="Branch predictor">branch predictor</a>.

Luckily, one of the more common patterns of code that normally relies on branching has a more elegant solution. Consider the following <a href="Pseudocode" title="Pseudocode">pseudocode</a>:<a href="#cite_note-rvinyard-1">[1]</a>

<div class="mw-highlight mw-highlight-lang-c mw-content-ltr" dir="ltr"><pre>if condition

{do_something}

else

{do_something_else}

</pre></div>

On a system that uses conditional branching, this might translate to <a href="Machine_language" class="mw-redirect" title="Machine language">machine instructions</a> looking similar to:<a href="#cite_note-rvinyard-1">[1]</a>

<div class="mw-highlight mw-highlight-lang-c mw-content-ltr" dir="ltr"><pre> branch_if_condition_to label1

do_something_else

branch_always_to label2

label1:

do_something

label2:

...

</pre></div>

With predication, all possible branch paths are coded inline, but some instructions execute while others do not. The basic idea is that each instruction is associated with a predicate (the word here used similarly to its usage in <a href="Predicate_logic" class="mw-redirect" title="Predicate logic">predicate logic</a>) and that the instruction will only be executed if the predicate is true. The machine code for the above example using predication might look something like this:<a href="#cite_note-rvinyard-1">[1]</a>

<div class="mw-highlight mw-highlight-lang-c mw-content-ltr" dir="ltr"><pre>(condition) do_something

(not condition) do_something_else

</pre></div>

Besides eliminating branches, less code is needed in total, provided the architecture provides predicated instructions. While this does not guarantee faster execution in general, it will if the <code>do_something</code> and <code>do_something_else</code> blocks of code are short enough.

Predication's simplest form is partial predication, where the architecture has conditional move or conditional select instructions. Conditional move instructions write the contents of one register over another only if the predicate's value is true, whereas conditional select instructions choose which of two registers has its contents written to a third based on the predicate's value. A more generalized and capable form is full predication. Full predication has a set of predicate registers for storing predicates (which allows multiple nested or sequential branches to be simultaneously eliminated) and most instructions in the architecture have an (optional) register specifier field to specify which predicate register supplies the predicate.<a href="#cite_note-2">[2]</a>

<div class="mw-heading mw-heading2"><h2 id="Advantages">Advantages</h2></div>

The main purpose of predication is to avoid jumps over very small sections of program code, increasing the effectiveness of <a href="Pipeline_(computing)" title="Pipeline (computing)">pipelined</a> execution and avoiding problems with the <a href="CPU_cache" title="CPU cache">cache</a>. It also has a number of more subtle benefits:

<ul><li>Functions that are traditionally computed using simple arithmetic and <a href="Bitwise_operation" title="Bitwise operation">bitwise operations</a> may be quicker to compute using predicated instructions.</li>

<li>Predicated instructions with different predicates can be mixed with each other and with unconditional code, allowing better <a href="Instruction_scheduling" title="Instruction scheduling">instruction scheduling</a> and so even better performance.</li>

<li>Elimination of unnecessary branch instructions can make the execution of necessary branches, such as those that make up loops, faster by lessening the load on <a href="Branch_prediction" class="mw-redirect" title="Branch prediction">branch prediction</a> mechanisms.</li>

<li>Elimination of the cost of a branch misprediction which can be high on deeply pipelined architectures.</li>

<li>Instruction sets that have comprehensive <a href="Condition_code_register" class="mw-redirect" title="Condition code register">Condition Codes</a> generated by instructions may reduce code size further by directly using the Condition Registers in or as predication.</li></ul>

<div class="mw-heading mw-heading2"><h2 id="Disadvantages">Disadvantages</h2></div>

Predication's primary drawback is in increased encoding space. In typical implementations, every instruction reserves a bitfield for the predicate specifying under what conditions that instruction should have an effect. When available memory is limited, as on <a href="Embedded_system" title="Embedded system">embedded devices</a>, this space cost can be prohibitive. However, some architectures such as <a href="Thumb-2" class="mw-redirect" title="Thumb-2">Thumb-2</a> are able to avoid this issue (see below). Other detriments are the following:<a href="#cite_note-Fisher04-3">[3]</a>

<ul><li>Predication complicates the hardware by adding levels of <a href="Control_unit" title="Control unit">logic</a> to critical <a href="Datapath" title="Datapath">paths</a> and potentially degrades clock speed.</li>

<li>A predicated block includes cycles for all operations, so shorter <a href="Control-flow_graph" title="Control-flow graph">paths</a> may take longer and be penalized.</li>

<li>An extra register read is required. A non-predicated ADD would read two registers from a register file, where a Predicated ADD would need to also read the predicate register file. This increases Hazards in <a href="Out-of-order_execution" title="Out-of-order execution">Out-of-order execution</a>.</li>

<li>Predication is not usually speculated and causes a longer dependency chain. For ordered data this translates to a performance loss compared to a predictable branch.<a href="#cite_note-4">[4]</a></li></ul>

Predication is most effective when paths are balanced or when the longest path is the most frequently executed,<a href="#cite_note-Fisher04-3">[3]</a> but determining such a path is very difficult at compile time, even in the presence of <a href="Profiling_(computer_programming)" title="Profiling (computer programming)">profiling information</a>.

<div class="mw-heading mw-heading2"><h2 id="History">History</h2></div>

Predicated instructions were popular in European computer designs of the 1950s, including the <a href="Mail%C3%BCfterl" title="Mailüfterl">Mailüfterl</a> (1955), the <a href="Z22_(computer)" title="Z22 (computer)">Zuse Z22</a> (1955), the <a href="ZEBRA_(computer)" title="ZEBRA (computer)">ZEBRA</a> (1958), and the <a href="Electrologica_X1" title="Electrologica X1">Electrologica X1</a> (1958). The <a href="ACS-1" class="mw-redirect" title="ACS-1">IBM ACS-1</a> design of 1967 allocated a "skip" bit in its instruction formats, and the CDC Flexible Processor in 1976 allocated three conditional execution bits in its microinstruction formats.

<a href="Hewlett-Packard" title="Hewlett-Packard">Hewlett-Packard</a>'s <a href="PA-RISC" title="PA-RISC">PA-RISC</a> architecture (1986) had a feature called nullification, which allowed most instructions to be predicated by the previous instruction. <a href="IBM" title="IBM">IBM</a>'s <a href="IBM_POWER_instruction_set_architecture" class="mw-redirect" title="IBM POWER instruction set architecture">POWER architecture</a> (1990) featured conditional move instructions. POWER's successor, <a href="PowerPC" title="PowerPC">PowerPC</a> (1993), dropped these instructions. <a href="Digital_Equipment_Corporation" title="Digital Equipment Corporation">Digital Equipment Corporation</a>'s <a href="DEC_Alpha" title="DEC Alpha">Alpha</a> architecture (1992) also featured conditional move instructions. <a href="MIPS_architecture" title="MIPS architecture">MIPS</a> gained conditional move instructions in 1994 with the MIPS IV version; and <a href="SPARC" title="SPARC">SPARC</a> was extended in Version 9 (1994) with conditional move instructions for both integer and floating-point registers.

In the <a href="Hewlett-Packard" title="Hewlett-Packard">Hewlett-Packard</a>/<a href="Intel" title="Intel">Intel</a> <a href="IA-64" title="IA-64">IA-64</a> architecture, most instructions are predicated. The predicates are stored in 64 special-purpose predicate <a href="Processor_register" title="Processor register">registers</a>; and one of the predicate registers is always true so that unpredicated instructions are simply instructions predicated with the value true. The use of predication is essential in IA-64's implementation of <a href="Software_pipelining" title="Software pipelining">software pipelining</a> because it avoids the need for writing separated code for prologs and epilogs.

In the <a href="X86" title="X86">x86</a> architecture, a family of conditional move instructions (<code>CMOV</code> and <code>FCMOV</code>) were added to the architecture by the <a href="Intel" title="Intel">Intel</a> <a href="Pentium_Pro" title="Pentium Pro">Pentium Pro</a> (1995) processor. The <code>CMOV</code> instructions copied the contents of the source register to the destination register depending on a predicate supplied by the value of the flag register.

In the <a href="ARM_architecture" class="mw-redirect" title="ARM architecture">ARM architecture</a>, the original 32-bit instruction set provides a feature called conditional execution that allows most instructions to be predicated by one of 13 predicates that are based on some combination of the four condition codes set by the previous instruction. ARM's <a href="ARM_architecture" class="mw-redirect" title="ARM architecture">Thumb</a> instruction set (1994) dropped conditional execution to reduce the size of instructions so they could fit in 16 bits, but its successor, <a href="ARM_architecture" class="mw-redirect" title="ARM architecture">Thumb-2</a> (2003) overcame this problem by using a special instruction which has no effect other than to supply predicates for the following four instructions. The 64-bit instruction set introduced in ARMv8-A (2011) replaced conditional execution with conditional selection instructions.

<div class="mw-heading mw-heading2"><h2 id="SIMD,_SIMT_and_vector_predication">SIMD, SIMT and vector predication</h2></div>

<div role="note" class="hatnote navigation-not-searchable">See also: <a href="Single_instruction%2C_multiple_threads" title="Single instruction, multiple threads">Single instruction, multiple threads</a></div>

Some <a href="SIMD_within_a_register" class="mw-redirect" title="SIMD within a register">SIMD within a register</a> instruction sets, like AVX2, have the ability to use a logical <a href="Mask_(computing)" title="Mask (computing)">mask</a> to conditionally load/store values to memory, in a parallel form of the conditional move. They may also apply individual mask bits to individual arithmetic units executing a parallel operation. One predicate mask bit is available for each sub-word of the SWAR register or each load/store value.

This form of multi-bit predication is also used in <a href="Vector_processors" class="mw-redirect" title="Vector processors">vector processors</a> at the element level (synonymous with SWAR sub-words):

<div class="mw-highlight mw-highlight-lang-c mw-content-ltr" dir="ltr"><pre>for each (sub-word i) of SWAR (or Vector) register

(condition-maskbit i) do_something(sub-word i)

(not condition-maskbit i) do_something_else(sub-word i)

</pre></div>

Masking is an integral part of <a href="Flynn's_taxonomy" title="Flynn's taxonomy">Array Processors</a> such as the <a href="ILLIAC_IV" title="ILLIAC IV">ILLIAC IV</a>. Array Processors are known today as <a href="Single_instruction%2C_multiple_threads" title="Single instruction, multiple threads">single instruction, multiple threads</a> (SIMT), and a predicate bit per PE used to activate or de-activate each Processing Element. When the PE has no <a href="SIMD_within_a_register" class="mw-redirect" title="SIMD within a register">SIMD within a register</a> instructions, each PE may be individually Predicated:

(active-maskbit j) broadcast_scalar_instruction_to(PE j)

</pre></div>

Modern SIMT <a href="GPUs" class="mw-redirect" title="GPUs">GPUs</a> use (or used, but ILLIAC IV documentation termed it <a href="ILLIAC_IV#Branches" title="ILLIAC IV">"branching"</a>) predication to enable/disable individual Processing Elements and, separately and furthermore, to also mask-out sub-words within any given PE's SWAR ALU.

<div class="mw-highlight mw-highlight-lang-c mw-content-ltr" dir="ltr"><pre>for each (PE j) of SIMT synchronously-concurrent array

(active-maskbit j) { // broadcast only to active SWAR PEs

for each (sub-word i) of SWAR register in (PE j)

}

</pre></div>

All the techniques, advantages and disadvantages of single scalar predication apply just as well to the parallel processing case, where the issues associated with branching are made far more complex.<a href="#cite_note-5">[5]</a>

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<ul><li><a href="Branch_predictor" title="Branch predictor">Branch predictor</a></li>

<li><a href="Control_flow" title="Control flow">Control flow</a></li>

<li><a href="Delay_slot" title="Delay slot">Delay slot</a></li>

<li><a href="Instruction-level_parallelism" title="Instruction-level parallelism">Instruction-level parallelism</a></li>

<li><a href="Optimizing_compiler" title="Optimizing compiler">Optimizing compiler</a></li>

<li><a href="Pipeline_stall" title="Pipeline stall">Pipeline stall</a></li>

<li><a href="Software_pipelining" title="Software pipelining">Software pipelining</a></li>

<li><a href="Speculative_execution" title="Speculative execution">Speculative execution</a></li>

<li><a href="Vector_processor" title="Vector processor">Vector processor</a></li>

<li><a href="Very_long_instruction_word" title="Very long instruction word">Very long instruction word</a></li></ul>

</div>

<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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</style><cite id="CITEREFRick_Vinyard2000" class="citation web cs1">Rick Vinyard (2000-04-26). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20150420152310/https://www.cs.nmsu.edu/~rvinyard/itanium/predication.htm">"Predication"</a>. cs.nmsu.edu. Archived from <a rel="nofollow" class="external text" href="https://www.cs.nmsu.edu/~rvinyard/itanium/predication.htm">the original</a> on 20 Apr 2015. Retrieved 2014-04-22.</cite>

</li>

<li id="cite_note-2"><a href="#cite_ref-2">^</a> <cite id="CITEREFMahlkeHankMcCormickAugust1995" class="citation conference cs1">Mahlke, Scott A.; Hank, Richard E.; McCormick, James E.; August, David I.; Hwn, Wen-mei W. (1995). A Comparison of Full and Partial Predicated Execution Support for ILP Processors. The 22nd International Symposium on Computer Architecture, 22–24 June 1995. <a href="CiteSeerX_(identifier)" class="mw-redirect" title="CiteSeerX (identifier)">CiteSeerX</a> <a rel="nofollow" class="external text" href="https://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.19.3187">10.1.1.19.3187</a>. <a href="Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F223982.225965">10.1145/223982.225965</a>. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>0-89791-698-0</bdi>.</cite>

</li>

<li id="cite_note-Fisher04-3">^ <a href="#cite_ref-Fisher04_3-0">a</a> <a href="#cite_ref-Fisher04_3-1">b</a> <cite id="CITEREFFisherFaraboschiYoung2004" class="citation book cs1">Fisher, Joseph A.; Faraboschi, Paolo; Young, Cliff (2004). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=DbOa0p1wRD4C&pg=PA172">"4.5.2 Predication § Predication in the Embedded Domain"</a>. Embedded Computing — A VLIW Approach to Architecture, Compilers, and Tools. Elsevier. p. 172. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>9780080477541</bdi>.</cite>

</li>

<li id="cite_note-4"><a href="#cite_ref-4">^</a> <cite id="CITEREFCordes" class="citation web cs1">Cordes, Peter. <a rel="nofollow" class="external text" href="https://stackoverflow.com/a/50960323">"assembly - How does Out of Order execution work with conditional instructions, Ex: CMOVcc in Intel or ADDNE (Add not equal) in ARM"</a>. Stack Overflow. <q>Unlike with control dependencies (branches), they don't predict or speculate what the flags will be, so a cmovcc instead of a jcc can create a loop-carried dependency chain and end up being worse than a predictable branch. <a rel="nofollow" class="external text" href="https://stackoverflow.com/questions/50959808">gcc optimization flag -O3 makes code slower than -O2</a> is an example of that.</q></cite> <code class="cs1-code">{{cite web}}</code>: External link in <code class="cs1-code"><code class="cs1-code">|quote=</code></code> (help)

</li>

<li id="cite_note-5"><a href="#cite_ref-5">^</a> <a rel="nofollow" class="external free" href="https://gpgpuarch.org/en/basic/simt/">https://gpgpuarch.org/en/basic/simt/</a>

</li>

</ol></div></div>

<div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2></div>

<ul><li><cite id="CITEREFClements2013" class="citation book cs1">Clements, Alan (2013). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=ySILAAAAQBAJ&pg=PA532">"8.3.7 Predication"</a>. Computer Organization & Architecture: Themes and Variations. Cengage Learning. pp. 532–9. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>978-1-285-41542-0</bdi>.</cite></li></ul></div><div><div class="zim-footer">

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